Dynamic power consumption is an ongoing concern for integrated circuit (IC) devices, especially with the ever-increasing clock frequencies used in synchronous IC devices. For some IC devices, more than half of the total dynamic power consumption may be attributed to clock distribution networks and flip-flop circuits. Many conventional flip-flops employ inverter circuits to generate complementary clock signals for use by various pass gates and/or tri-state circuits that form the latches and/or gating circuits within the flip-flops. These inverter circuits, as well as the pass gates and tri-state circuits, consume dynamic power every time the clock signal transitions between logic states. As a result, these conventional flip-flops may consume a significant amount of dynamic power even when switching activity is relatively low.
For example, FIG. 1 shows a conventional data flip-flop circuit 100 that includes a first latch 1 10, a second latch 120, a clock inversion circuit 130, and inverters INVO and INV3. The first latch 1 10 may operate as the “master” latch, and the second latch 120 may operate as the “slave” latch. The first latch 1 10 includes a first pass gate PG1 and a first storage cell 1 1 1 formed by cross-coupled inverters INV1 a and INV1 b. The second latch 120 includes a second pass gate PG2 and a second storage cell 121 formed by cross-coupled inverters INV2a and INV2b. The clock inversion circuit 130, which is to generate complementary clock signals for pass gates PG1-PG2 and for tri-state inverters INV1 b and INV2b within respective latches 1 10 and 120, includes two series-connected inverters INV4a and INV4b. For example, a clock signal CLK is provided to an input of inverter INV4a, which inverts (e.g., logically complements) CLK to generate an inverted network clock signal CLKn. The inverted network clock signal CLKn is inverted by inverter INV4b to generate the network clock signal CLKn. Thus, the clock signal CLKn is the logical complement of the clock signal CLKn.
The data signal (D) is inverted by inverter INV0 and provided as a complemented data signal D to first pass gate PG1. The first pass gate PG1 includes a control terminal to receive CLKn, and includes an inverted (e.g., complementary) control terminal to receive CLKn. The inverter INV1b is depicted as a tri-state inverter that includes an enable terminal to receive CLKn and includes an inverted enable terminal to receive CLKn. The output terminal of first latch 110 is coupled to second pass gate PG2.
The second pass gate PG2 includes a control terminal to receive CLKn, an inverted (e.g., complementary) control terminal to receive CLKn, and an output terminal coupled to the second storage element 121 The inverter INV2b is depicted as a tri-state inverter that includes an enable terminal to receive CLKn and includes an inverted (e.g., complementary) enable terminal to receive CLKn.
When CLK is in a logic low state, inverter INV4a drives CLKn to a logic high state, and inverter INV4b drives CLKn to the logic low state. In response thereto, pass gate PG1 turns on and passes the value of D to first latch 1 10, which stores the value of D. The logic low state of CLKn and the logic high state of CLKn turn off second pass gate PG2, thereby isolating the second latch 120 from the first latch 1 10.
When CLK transitions to logic high, inverter INV4a drives CLKn to logic low, and inverter INV4b drives CLKn to logic high. In response thereto, pass gate PG1 turns off and isolates first latch 110 from the input signal D, and second pass gate PG2 turns on and passes the value of D from first latch 110 to second latch 120. The second latch 120 stores the value of D, which is inverted by inverter INV3 and provided as the flip-flop output signal Q so that Q=D.
The inverters INV4a-INV4b that generate the complementary clock signals CLKn and CLKn consume dynamic power every time the input clock signal CLK transitions between logic states, which is undesirable. In addition, because the pass gates PG1-PG2 and the tri-state inverters INV1b and INV2b are clocked by both CLKn and its complement CLKn, the pass gates PG1-PG2 and the latches 110 and 120 consume dynamic power every time the clock signal transitions between logic states, which is also undesirable.
Thus, there is a need to reduce the dynamic power consumption associated with flip-flop circuits.